`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    02:36:52 05/02/2013 
// Design Name: 
// Module Name:    ALU 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ALU(
	 input clk_50Mhz,
	 input reset_b,
    input sum,
    input cmp,
    input mul,
    input [3:0]regA,
    input [3:0]regB,
    output reg [7:0]result,
	 output o_pulse
    );

	reg [7:0]temp;
	reg temp2;
	reg [3:0]counter;
	reg flag;


	always@(posedge clk_50Mhz, negedge reset_b) begin

		if(reset_b ==1'b0) begin
		end		
	
		/*For sum case*/		
		else if(sum==1'b1) begin
			 result = regA+regB; 
		flag=1;		
				
		end// end sum
		
	
		/*For cmp case*/
		else if(cmp==1'b1) begin
			if(regA==regB) begin
				 result =1;
			end
			
			else begin
				 result =0;
			end
			flag=1;	
		end //end cmp
	
		/*For mul case*/
		else if(mul==1'b1) begin
			 result = regA*regB;
			flag=1;
		end	 
		
		else begin
			flag=0;
		end
	end	

	PED result_pulse( .i_signal(flag) , .i_clk(clk_50Mhz), .i_rst_b(reset_b), .o_pulse(o_pulse)); 

endmodule



